Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.

Journal article

As a first step, most model checkers used in the hardware industry convert a high-level register-transfer-level (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels and, thus, are less scalable. The RTL of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. This paper uses predicate abstraction, a software verification technique, for verifying RTL Verilog. There are two challenges when applying predicate abstraction to circuits: 1) the computation of the abstract model in presence of a large number of predicates and 2) the discovery of suitable word-level predicates for abstraction refinement. We address the first problem using a technique called predicate clustering. We address the second problem by computing the weakest preconditions of Verilog statements in order to obtain new word-level predicates during abstraction refinement. We compare the performance of our technique with localization reduction, a netlist-level abstraction technique, and report improvements on a set of benchmarks. © 2008 IEEE.

Authors: Jain, H; Kroening, D; Sharygina, N; Clarke, E

• Publication status: Published
• Journal: IEEE Trans. on CAD of Integrated Circuits and Systems
• Volume: 27
• Issue: 2
• Pages: 366-379
• Publication date: 2008-01-01
• DOI: 10.1109/TCAD.2007.907270
• EISSN: 1937-4151
• ISSN: 0278-0070
• Language: English
• Keywords: verification; refinement; predicate abstraction; satisfiability (SAT); register transfer level (RTL); model checking (MC)