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Relieving capacity limits on FPGA−based SAT−solvers

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APA Style

Haller, L., & Singh, S. (2010). Relieving capacity limits on FPGA−based SAT−solvers.

MLA Style

Haller, L, and S Singh. “Relieving Capacity Limits on FPGA−Based SAT−Solvers.” 2010.

Chicago Style

Haller, L, and S Singh. 2010. “Relieving Capacity Limits on FPGA−Based SAT−Solvers.”
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Authors

+ Haller, L More by this author

Role:: Author

+ Singh, S More by this author

Role:: Author

Host title:: FMCAD
Publication date:: 2010-01-01

UUID:: uuid:60a1d083-24d2-4cfe-b133-d0dbcb1f42ef
Local pid:: cs:5288
Deposit date:: 2015-03-31
ARK identifier:: ark:/29072/ora_60a1d08324d24cfeb133d0dbcb1f42ef

Terms of use

Copyright date:: 2010

Licence:: Terms and Conditions of Use for Oxford University Research Archive

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