Performance of the beetle readout chip for LHCb

Conference item

This paper details the development steps of the 128 channel pipelined readout chip Beetle, which is being designed for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors(1) of LHCb. Section II. summarizes the Beetle chip architecture.Section III. shows the key measurements on the first chip version (Beetle 1.0) which drove the design changes for the Beetle 1.1. First performance data of the new chip is presented in section IV., while an outlook on the future test and development of the chip are given in section V.

Authors: van Bakel, N; van den Brand, J; Verkooijen, H; Baumeister, D; Hofmann, W

• Publication status: Published
• Journal: PROCEEDINGS OF THE SEVENTH WORKSHOP ON ELECTRONICS FOR LHC EXPERIMENTS
• Volume: 2001
• Issue: 5
• Pages: 52-56
• Publication date: 2001-01-01
• Event title: 7th Workshop on Electronics for LHC Experiments
• ISSN: 0007-8328