Conference item
Trading latency for compute in the network
- Abstract:
- This paper proposes a new heterogeneous approach to programmable architecture that extends the capabilities of programmable switch ASICs with FPGAs. It identifies the key challenges in building a heterogeneous network architecture, and presents a concrete design and implementation based around a proof-of-concept data deduplication application. Our prototype demonstrates the use of a programmable network switch and FPGAs to accelerate storage fingerprinting, running at 10G and 100G at line rate. Our approach is modular, scalable and generalizes to a wide range of applications.
- Publication status:
- Published
- Peer review status:
- Peer reviewed
Actions
Access Document
- Files:
-
-
(Preview, Accepted manuscript, 475.3KB, Terms of use)
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- Publisher copy:
- 10.1145/3405672.3405807
- Publication website:
- https://dl.acm.org/doi/proceedings/10.1145/3405672
Authors
- Publisher:
- Association for Computing Machinery
- Host title:
- NAI '20: Proceedings of the Workshop on Network Application Integration/CoDesign
- Pages:
- 35–40
- Publication date:
- 2020-08-14
- Acceptance date:
- 2020-06-02
- Event title:
- ACM SIGCOMM 2020 Workshop on Network Application Integration/CoDesign (NAI 2020)
- Event website:
- https://conferences.sigcomm.org/sigcomm/2020/workshop-nai.html
- Event start date:
- 2020-08-14
- Event end date:
- 2020-08-14
- DOI:
- ISBN:
- 9781450380447
- Language:
-
English
- Keywords:
- Pubs id:
-
1115895
- Local pid:
-
pubs:1115895
- Deposit date:
-
2020-07-02
Terms of use
- Copyright holder:
- Association for Computing Machinery
- Copyright date:
- 2020
- Rights statement:
- © 2020 Association for Computing Machinery.
- Notes:
- This paper was presented at the ACM SIGCOMM 2020 Workshop on Network Application Integration/CoDesign (NAI 2020), 14 August 2020.
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