A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process

Conference item

For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000/575 μA/μm, respectively, have been achieved at 1 nA/μm off-current and 1.1V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements. © 2008 IEEE.

Authors: Chen, X; Samavedam, S; Narayanan, V; Stein, K; Hobbs, C

• Host title: Digest of Technical Papers - Symposium on VLSI Technology
• Pages: 88-89
• Publication date: 2008-01-01
• DOI: 10.1109/VLSIT.2008.4588573
• ISSN: 0743-1562
• ISBN: 9781424418053