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Thesis

Precise abstract interpretation of hardware designs

Abstract:

This dissertation shows that the bounded property verification of hardware Register Transfer Level (RTL) designs can be efficiently performed by precise abstract interpretation of a software representation of the RTL.

The first part of this dissertation presents a novel framework for RTL verification using native software analyzers. To this end, we first present a translation of the hardware circuit expressed in Verilog RTL into the software in C called the software netlist

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Division:
MPLS
Department:
Computer Science
Role:
Author

Contributors

Department:
University of Oxford
Role:
Supervisor
Department:
University of Oxford
Role:
Supervisor
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Name:
Semiconductor Research Corporation
Funding agency for:
Mukherjee, R
Type of award:
DPhil
Level of award:
Doctoral
Awarding institution:
University of Oxford
Keywords:
Subjects:
UUID:
uuid:680f0093-0405-4a0b-88dc-c4d7177d840f
Deposit date:
2018-06-18

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