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Programmable hardware architectures for sensor validation

Abstract:

A previous paper (Henry, 1995a) introduced the technique of hardware compilation as the basis for developing highly flexible programmable hardware platforms for control applications such as sensor validation. This paper describes two PC-hosted architectures for sensor validation research. The first holds up to two FPGAs and supports a daughter board with application-specific circuitry. The second is based on the transputer TRAM standard, and consists of programmable hardware modules providing...

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Publication status:
Published
Peer review status:
Peer reviewed
Version:
Accepted manuscript

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Publisher copy:
10.1016/0967-0661(96)00144-X

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Department:
Oxford, MPLS, Engineering Science
Clarke, DW More by this author
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Publisher:
Elsevier Ltd. Publisher's website
Journal:
Control Engineering Practice
Volume:
4
Issue:
10
Pages:
1339-1354
Publication date:
1999-04-30
DOI:
ISSN:
0967-0661
Pubs id:
pubs:64886
URN:
uri:52238b38-8659-42e0-8a97-6632457c93c4
UUID:
uuid:52238b38-8659-42e0-8a97-6632457c93c4
Local pid:
pubs:64886

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