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Correctness of a Fault−Tolerant Real−Time Scheduler and its Hardware Implementation

Abstract:

We formalize the correctness of a fault-tolerant scheduler in a time-triggered architecture. Where previous research elaborated on real-time protocol correctness, we extend this work to gate-level hardware. This requires a sophisticated analysis of analog bit-level synchronization and transmission. Our case-study is a concrete automotive bus controller (ABC), inspired by the FlexRay standard. For a set of interconnected ABCs, vulnerable to sudden failure, we prove at gate-level, that all oper...

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Publisher copy:
10.1109/MEMCOD.2008.4547708
Publisher:
IEEE
Host title:
Sixth ACM and IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'08)
Publication date:
2008-06-01
DOI:
ISBN:
9781424424177
UUID:
uuid:1c1ea9dd-1672-40c2-9655-907f95dc9be4
Local pid:
cs:1377
Deposit date:
2015-03-31

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