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KEYNOTE PAPER - HARDWARE COMPILATION - A NEW TECHNIQUE FOR RAPID PROTOTYPING OF DIGITAL-SYSTEMS APPLIED TO SENSOR VALIDATION

Publication status:: Published

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APA Style

Henry, M. (1995). KEYNOTE PAPER - HARDWARE COMPILATION - A NEW TECHNIQUE FOR RAPID PROTOTYPING OF DIGITAL-SYSTEMS APPLIED TO SENSOR VALIDATION. CONTROL ENGINEERING PRACTICE, 3(7), 907–924.

MLA Style

Henry, M. “KEYNOTE PAPER - HARDWARE COMPILATION - A NEW TECHNIQUE FOR RAPID PROTOTYPING OF DIGITAL-SYSTEMS APPLIED TO SENSOR VALIDATION.” CONTROL ENGINEERING PRACTICE, vol. 3, no. 7, 1995, pp. 907–24.

Chicago Style

Henry, M. 1995. “KEYNOTE PAPER - HARDWARE COMPILATION - A NEW TECHNIQUE FOR RAPID PROTOTYPING OF DIGITAL-SYSTEMS APPLIED TO SENSOR VALIDATION.” CONTROL ENGINEERING PRACTICE 3 (7): 907–24.
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Publisher copy:: 10.1016/0967-0661(95)00074-5

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Bibliographic Details

Journal:: CONTROL ENGINEERING PRACTICE
Volume:: 3
Issue:: 7
Pages:: 907-924
Publication date:: 1995-07-01
DOI:: 10.1016/0967-0661(95)00074-5
ISSN:: 0967-0661

Item Description

Keywords:: HANDEL

FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)

TRANSPUTER

FAULT DETECTION AND DIAGNOSIS

UNCERTAINTY

OCCAM

FIELDBUS

HARDWARE COMPILATION

SENSOR VALIDATION
Pubs id:: pubs:64835
UUID:: uuid:135abd0a-859f-4dbd-86af-9806218ca4ab
Local pid:: pubs:64835
Source identifiers:: 64835
Deposit date:: 2013-11-17

Terms of use

Copyright date:: 1995

Licence:: Terms and Conditions of Use for Oxford University Research Archive

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