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Image Computation and Predicate Refinement for RTL Verilog using Word Level Proofs

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APA Style

Kroening, D., & Sharygina, N. (2007). Image Computation and Predicate Refinement for RTL Verilog using Word Level Proofs.

MLA Style

Kroening, D, and N Sharygina. “Image Computation and Predicate Refinement for RTL Verilog Using Word Level Proofs.” 2007.

Chicago Style

Kroening, D, and N Sharygina. 2007. “Image Computation and Predicate Refinement for RTL Verilog Using Word Level Proofs.”
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Authors

+ Kroening, D More by this author

Role:: Author

+ Sharygina, N More by this author

Role:: Author

Host title:: Proceedings of DATE 2007
Publication date:: 2007-01-01

UUID:: uuid:109d8908-421f-4487-8122-f69c98a7576a
Local pid:: cs:714
Deposit date:: 2015-03-31
ARK identifier:: ark:/29072/ora_109d8908421f44878122f69c98a7576a

Terms of use

Copyright date:: 2007

Licence:: Terms and Conditions of Use for Oxford University Research Archive

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