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PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

Abstract:

The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift cloc...

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Publisher copy:
10.1109/ICSJ.2012.6523460

Authors


Host title:
2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
Publication date:
2012-01-01
DOI:
ISBN:
9781467326551
Pubs id:
pubs:411670
UUID:
uuid:084cca8c-7309-4d33-83c6-b5e25bdee09b
Local pid:
pubs:411670
Source identifiers:
411670
Deposit date:
2013-11-17

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