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Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures

Abstract:

Plug-n-play-style intellectual property reuse in system-on-chip design is facilitated by the use of an on-chip bus architecture. Component integration and verification in such systems is a cumbersome and time consuming process largely concerned with interfacing issues. A synchronous, finite state machine framework for modelling communication aspects of such architecture is presented. The framework has been developed via interaction with designers and the industry, and is intuitive and light-w...

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Publisher copy:
10.1049/ip-cdt:20045097

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Contributors

Role:
Editor
Journal:
IEE Proceedings − Computers and Digital Techniques
Volume:
152
Issue:
1
Pages:
20-27
Publication date:
2005-01-01
DOI:
UUID:
uuid:0355c431-b13f-4869-8c63-141236209e51
Local pid:
cs:3098
Deposit date:
2015-03-31

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