Journal article
Area Optimisation for Field−Programmable Gate Arrays in SystemC Hardware Compilation
- Abstract:
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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between mult...
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Bibliographic Details
- Journal:
- International Journal of Reconfigurable Computing
- Publication date:
- 2008-01-01
- DOI:
Item Description
- UUID:
-
uuid:e0ced6e9-409f-45da-9c8c-5b37995e45a3
- Local pid:
- cs:5394
- Deposit date:
- 2015-03-31
Terms of use
- Copyright date:
- 2008
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