Journal article
Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC
- Abstract:
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Obtaining highly accurate depth from stereo images in real time has many applications across computer vision and robotics, but in some contexts, upper bounds on power consumption constrain the feasible hardware to embedded platforms such as FPGAs. Whilst various stereo algorithms have been deployed on these platforms, usually cut down to better match the embedded architecture, certain key parts of the more advanced algorithms, e.g., those that rely on unpredictable access to memory or are hig...
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- Publication status:
- Published
- Peer review status:
- Peer reviewed
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- Files:
-
-
(Accepted manuscript, pdf, 263.8KB)
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- Publisher copy:
- 10.1109/TCSII.2019.2909169
Authors
Funding
Bibliographic Details
- Publisher:
- IEEE Publisher's website
- Journal:
- IEEE Transactions on Circuits and Systems II: Express Briefs Journal website
- Volume:
- 66
- Issue:
- 5
- Pages:
- 773-777
- Publication date:
- 2019-04-03
- Acceptance date:
- 2019-03-25
- DOI:
- EISSN:
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1558-3791
- ISSN:
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1549-7747
- Source identifiers:
-
999316
Item Description
- Keywords:
- Pubs id:
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pubs:999316
- UUID:
-
uuid:cc337c7a-70ff-49f8-a9f9-5f43a34d9805
- Local pid:
- pubs:999316
- Deposit date:
- 2019-06-17
Terms of use
- Copyright holder:
- IEEE
- Copyright date:
- 2019
- Notes:
- Copyright © 2019 IEEE. This is the accepted manuscript version of the article. The final version is available online from IEEE at: http://dx.doi.org/10.1109/TCSII.2019.2909169
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