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A heuristic and an exact method for the gate matrix connection cost minimization problem

Abstract:

In many applications, a sequencing of patterns (electronic circuit nodes, cutting patterns, product orders, etc.) has to be found in order to optimize some given objective function, giving rise to the so-called open stack problems. We focus on a problem related to the optimization of gate matrix layouts: electronic circuits are obtained by connecting gates and one seeks a gate layout permutation that minimizes connection costs under restrictions on the circuit area. In the literature, the con...

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Publisher copy:
10.1111/itor.12025

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Journal:
International Transactions in Operational Research
Volume:
20
Issue:
5
Pages:
627-643
Publication date:
2013-09-05
DOI:
EISSN:
1475-3995
ISSN:
0969-6016
URN:
uuid:bb8e6666-ac2e-44ff-9053-7fbafaa644fa
Source identifiers:
417257
Local pid:
pubs:417257

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