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ATPG for reversible circuits using technology−related fault models

Abstract:

We address the problem of test set generation and test set reduction, to first detect, and later localize faults occurring in reversible circuits. Reversible Computation has high promise of low power consumption. Some new fault models are first presented here. An explanation of the new fault models is made based on a physical realization representing the state of the art in the reversible CMOS circuit technology. Evidence is then presented showing that the fault models presented in the curren...

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Publisher copy:
10.1.1.83.6049(
Journal:
Proc. 7th International Symposium on Representations and Methodology of Future Computing Technologies More from this journal
Pages:
8
Publication date:
2005-09-01
DOI:
UUID:
uuid:ad6fcf15-fb3c-46cd-9610-298084a2ad93
Local pid:
cs:4049
Deposit date:
2015-03-31

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