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Specifying and verifying systems with multiple clocks

Abstract:
Multiple clock domains are a challenge for hardware specification and verification. We present a method for specifying the relations between multiple clocks, and for modeling the possible behaviors. We can then verify a hardware design assuming that the clocks meet these constraints. We implement our ideas in the context of SAT based bounded model checking (BMC), using ANSI-C programs to specify the functional behavior of the design.
Publication status:
Published
Peer review status:
Peer reviewed

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Publisher copy:
10.1109/ICCD.2003.1240872

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Institution:
University of Oxford
Division:
MPLS
Department:
Computer Science
Role:
Author
Publisher:
IEEE
Host title:
Proceedings 21st International Conference on Computer Design
Journal:
Proceedings 21st International Conference on Computer Design More from this journal
Pages:
48-55
Publication date:
2003-12-02
DOI:
ISBN:
0769520251
Keywords:
Pubs id:
pubs:327199
UUID:
uuid:a7772414-bdf9-4649-ae41-14a7b467e3f9
Local pid:
pubs:327199
Source identifiers:
327199
Deposit date:
2017-01-28

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