Thesis icon

Thesis

Technology mapping of heterogeneous lookup table based field programmable gate arrays

Abstract:

A lot of work has been done over the last decade on the logic synthesis and technology mapping of field programmable gate arrays (FPGAs) based on a single size of lookup table (LUT). A significant part of the FPGA market is occupied by devices based on more than one type of lookup tables. Examples of these heterogeneous LUT-based FPGAs are the Xilinx 4000 series devices. The technology mapping for this class of FPGAs has hardly been considered. This thesis covers work on the synthesis for...

Expand abstract

Actions


Access Document


Files:

Authors


More by this author
Department:
Programming Research Group
Publication date:
1998
Type of award:
DPhil
Level of award:
Doctoral
Awarding institution:
University of Oxford
Barcode:
603826269
URN:
uuid:8ec8745f-c0b2-43c0-994f-bd949d9fdefa
Local pid:
td:603826269

Terms of use


Metrics



If you are the owner of this record, you can report an update to it here: Report update to this record

TO TOP