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V2c – A Verilog to C translator

Abstract:
We present v2c, a tool for translating Verilog to C. The tool accepts synthesizable Verilog as input and generates a word-level C program as an output, which we call the software netlist. The generated program is cycle-accurate and bit precise. The translation is based on the synthesis semantics of Verilog. There are several use cases for v2c, ranging from hardware property verification, coverification to simulation and equivalence checking. This paper gives details of the translation and demonstrates the utility of the tool.
Publication status:
Published
Peer review status:
Peer reviewed

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Publisher copy:
10.1007/978-3-662-49674-9_38

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Institution:
University of Oxford
Oxford college:
Balliol College
Role:
Author
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Institution:
University of Oxford
Division:
MPLS
Department:
Computer Science
Role:
Author
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Name:
Semiconductor Research Corporation
Grant:
2269.001
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Name:
European Research Council
Grant:
280053
Publisher:
Springer
Host title:
Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2016) in Lecture Notes in Computer Science
Journal:
Lecture Notes in Computer Science More from this journal
Volume:
9636
Pages:
580-586
Publication date:
2016-04-01
Acceptance date:
2015-12-18
DOI:
ISSN:
0302-9743 and 1611-3349
ISBN:
9783662496732
Pubs id:
pubs:619144
UUID:
uuid:69904a82-7de8-47f7-8208-899789a28d9d
Local pid:
pubs:619144
Source identifiers:
619144
Deposit date:
2017-01-28

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