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Design of a readout chip for LHCB

Abstract:
This paper details design and simulation of a prototype of a 128 channel readout chip for the LHCb experiment.The chip named Beetle fulfills the requirements of the silicon vertex detector, the inner tracker, the pileup veto trigger and the RICH detector(1) of LHCb.Section 1 summarizes the requirements on a LHCb frontend chip. Section 2 presents an overview of the chip's architecture and features. Section 3 describes the various components and shows simulation results. Section 4 gives an outlook on future plans.
Publication status:
Published

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Volume:
2000
Issue:
10
Pages:
157-160
Publication date:
2000-01-01
ISSN:
0007-8328
URN:
uuid:5f4977fa-32bd-4d14-ac09-fd76185d2f91
Source identifiers:
28840
Local pid:
pubs:28840
ISBN:
92-9083-172-3

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