Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Tseng, J-C; Chen, Y-L; Hsu, C-T; Tsai, F-Y; Chen, P-A; Ker, M-D; IEEE, EDSRG

Abstract:

An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

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APA Style

Tseng, J.-C., Chen, Y.-L., Hsu, C.-T., Tsai, F.-Y., Chen, P.-A., Ker, M.-D., & IEEE, E. D. S. R. G. (2008). Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits. 625–626.

MLA Style

Tseng, J.-C., et al. Mechanism of Snapback Failure Induced by the Latch-up Test in High-Voltage CMOS Integrated Circuits. 2008, pp. 625–26.

Chicago Style

Tseng, J-C, Y-L Chen, C-T Hsu, F-Y Tsai, P-A Chen, M-D Ker, and EDSRG IEEE. 2008. “Mechanism of Snapback Failure Induced by the Latch-up Test in High-Voltage CMOS Integrated Circuits.” In , 625–26.
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Authors

Tseng, J-C More by this author

Chen, Y-L More by this author

Hsu, C-T More by this author

Tsai, F-Y More by this author

Chen, P-A More by this author

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Bibliographic Details

Pages:: 625-626
Publication date:: 2008
URN:: uuid:3c329cfc-cb6c-4d87-8e4a-f63a4bca7428
Source identifiers:: 21710
Local pid:: pubs:21710
ISBN:: 978-1-4244-2049-0

Item Description

Keywords:: EOS

latch-up

ESD

high-voltage

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License:: Terms and Conditions of Use for Oxford University Research Archive

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