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Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Abstract:
An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.
Publication status:
Published

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Authors


Tseng, J-C More by this author
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Pages:
625-626
Publication date:
2008
URN:
uuid:3c329cfc-cb6c-4d87-8e4a-f63a4bca7428
Source identifiers:
21710
Local pid:
pubs:21710
ISBN:
978-1-4244-2049-0

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