Conference item icon

Conference item

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Abstract:
An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.
Publication status:
Published

Actions


Authors


Expand authors...
Journal:
2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL
Pages:
625-626
Publication date:
2008-01-01
Event title:
46th Annual IEEE International Reliability Physics Symposium
Source identifiers:
21710
ISBN:
9781424420490
Keywords:
Pubs id:
pubs:21710
UUID:
uuid:3c329cfc-cb6c-4d87-8e4a-f63a4bca7428
Local pid:
pubs:21710
Deposit date:
2012-12-19

Terms of use


Views and Downloads






If you are the owner of this record, you can report an update to it here: Report update to this record

TO TOP