- Abstract:
- A novel, low power frequency synthesiser system with 60MHz output bandwidth is reported which is suitable for integration in a single chip RF transceiver. The system is based upon a conventional DDFS architecture. However, the problems which usually arise from the non-ideal-behaviour of the DAC and the high power consumption of a ROM are avoided by using a non-volatile analogue memory array. Simulation results are presented which show that the system is suitable for use in an RF transceiver.
- Publication status:
- Published
- Publisher copy:
- 10.1109/VTSA.2001.934481
-
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- Pages:
- 53-56
- Publication date:
- 2001
- DOI:
- URN:
-
uuid:3c32068b-406e-45f6-99aa-b25665434af4
- Source identifiers:
-
64506
- Local pid:
- pubs:64506
- ISBN:
- 0-7803-6412-0
- Copyright date:
- 2001
Conference
A 200MHz analogue-ROM based direct digital frequency synthesiser with amplitude modulation
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