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Pipeline quantum processor architecture for silicon spin qubits

Abstract:

We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling N-qubit states through a large layered physical array of structures which realise quantum logic gates in stages. Thus, the circuit depth corresponds to the number of layers of structures. Subsequen...

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Publication status:
Published
Peer review status:
Peer reviewed

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Publisher copy:
10.1038/s41534-024-00823-y

Authors


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Institution:
University of Oxford
Division:
MPLS
Department:
Materials
Role:
Author
ORCID:
0000-0001-5659-4301
More by this author
Institution:
University of Oxford
Division:
MPLS
Department:
Materials
Role:
Author
ORCID:
0000-0002-7766-5348
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Grant:
EP/L015242/1
Programme:
Centre for Doctoral Training in Delivering Quantum Technologies
Publisher:
Springer Nature
Journal:
npj Quantum Information More from this journal
Volume:
10
Issue:
1
Article number:
31
Publication date:
2024-03-12
Acceptance date:
2024-02-15
DOI:
EISSN:
2056-6387
Language:
English
Keywords:
Pubs id:
1836603
Local pid:
pubs:1836603
Deposit date:
2024-04-25

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