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Assume-guarantee validation for STE properties within an SVA environment

Abstract:

Symbolic Trajectory Evaluation is an industrial-strength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor execution units. These correctness results are typically obtained under certain assumptions about how the verified hardware block's inputs are driven, as well as assumptions about the values of these inputs. For correct overall operation, the hardware environment within which the verifie...

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Publisher copy:
10.1109/FMCAD.2009.5351133

Authors


Khasidashvili, Z More by this author
Gavrielov, G More by this author
Pages:
108-115
Publication date:
2009-12-07
DOI:
URN:
uuid:20baa393-a357-4947-804a-e7eaa8b08f52
Source identifiers:
328690
Local pid:
pubs:328690
ISBN:
9781424449668

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