Conference item
Automated pipeline design
- Abstract:
- The interlock and forwarding logic is considered the tricky part of fully-featured piplined microprocessor and especially debugging these parts delays the hardware design process considerably. It is therefore desirable to automate the design of both interlock and forwarding logic. The hardware design engineer begins with a sequential implementation without any interlock and forwarding logic. A tool then adds the forwarding and interlock logic required for pipelining. This paper describes the algorithm for such a tool and the correctness is formally verified. We use a standard DLX RISC processor as an example.
- Publication status:
- Published
- Peer review status:
- Peer reviewed
Actions
Access Document
- Files:
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(Preview, Version of record, pdf, 82.5KB, Terms of use)
-
- Publisher copy:
- 10.1145/378239.379071
Authors
- Publisher:
- ACM
- Host title:
- Proceedings of the 38th Annual Design Automation Conference
- Journal:
- Proceedings of the 38th Annual Design Automation Conference More from this journal
- Pages:
- 810-815
- Publication date:
- 2001-01-01
- DOI:
- ISSN:
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0738-100X
- ISBN:
- 1581132972
- Keywords:
- Pubs id:
-
pubs:327202
- UUID:
-
uuid:1979c692-dc60-45b7-b41f-a1b7fdced398
- Local pid:
-
pubs:327202
- Source identifiers:
-
327202
- Deposit date:
-
2017-01-28
Terms of use
- Copyright holder:
- ACM
- Copyright date:
- 2001
- Notes:
- Copyright © 2001 ACM
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